MOSIS 2.0 Director

Background

The California Defense Ready Electronics and Microdevices Superhub (California DREAMS) has been launched to accelerate the development and prototyping of advanced RF and supporting technologies for electronic warfare, 5G/6G, and the broader technical areas of the Department of Defense Microelectronics Commons Program.

Led by the University of Southern California Information Sciences Institute (ISI), California DREAMS consists of seventeen partners and a growing team of affiliates. This team has come together to establish a unique rapid prototyping capability across our network of seven university nanofabrication facilities (USC, UCI, UCLA, UCR, UCSB, UCSD, and Caltech) and three DoD-volume fabs (Northrop Grumman, Teledyne, and HRL Laboratories) within the Southern California area.

MOSIS 2.0 builds on our 40+ year legacy of providing Multi-Project Wafer (MPW) services through MOSIS, expanding our capabilities by offering comprehensive semiconductor prototyping solutions through an extensive network of partners, including seven university nanofabs, three DOD-volume fabs, and seven commercial foundries. MOSIS 2.0 serves as the storefront and engineering services for the hub and will be self-sustaining.

More information on California DREAMS and MOSIS 2.0 is available online.

Location

This position is on-site in Marina del Rey, CA, with regular engagements to our partners and affiliates across the Southern California area.

Position Responsibilities

The MOSIS 2.0 Director will work across the CA Dreams Leadership Team and the Technical Steering Committee, responsibilities include the following.

• Building a revenue pipeline of client engagements across industry, government, and academia that leads to a fully self-sustaining and growing service
• Leading day-to-day operational management of the MOSIS 2.0 team to supply tapeout services with commercial foundries as well as prototyping services with leading nanofabs
• Instituting organizational processes and practices that enable the scaling of the MOSIS 2.0 service with a focus on customer engagement and retention
• Identifying and deploying new technical services and offerings based on market needs

Preferred Qualifications

• US citizenship, clearable to Top Secret
• 5+ years of experience leading business units with profit/loss responsibility, establishing and driving a vision to grow sales and revenue
• 10+ years of experience with federal and private sector programs and semiconductor clients
• 10+ years of experience leading semiconductor engineering teams and foundries

Minimum Education

Advanced degree in electrical engineering

Minimum Experience

• A recognized leader in the semiconductor industry with recognition across government semiconductor sponsors.
• Demonstrated record of semiconductor business success in building and supporting long-term revenue pipelines, and leading organizations with government and commercial clients.
• Demonstrated technical leadership and successful team building resulting in industry team leadership.
• Exceptional communication skills across internal teams, partners, sponsors, and clients

EDA Infrastructure Engineer

The MOSIS 2.0 PIES Team is Hiring

Background

The California Defense Ready Electronics and Microdevices Superhub (California DREAMS) will promote innovation and lab-to-fab transition for RF and other technologies in the Southern California region. MOSIS 2.0 will play a critical role in providing access to university nanofabs and industry prototyping and production fabs in support of rapid prototyping for Government- and Industry-funded R&D projects. The primary end uses for the service span from advanced RF-spectrum communications and sensing applications such as 5G/6G and related domains to advanced digital design. The Prototype Integration and Engineering Services (PIES) team will operate within MOSIS 2.0 to provide engineering support for users bridging the valley between innovations and production.

MOSIS 2.0 PIES team is hiring an EDA Infrastructure Engineer that will be part of a core team at USC/ISI complemented by a distributed team at our partner university labs and industry fabs.

Location

California (On-site at the USC University Park Campus)

Position Type

Full-Time, Research/Support Role, MOSIS 2.0 (California DREAMS Microelectronics Commons) / USC ECE Department.

Key responsibilities

• Maintaining EDA tool flows for tools from multiple vendors
• Managing cloud platform for EDA tool usage and IP repository
• Managing EDA license usage
• Support internal and external EDA users
• Develop collaborative cloud-based EDA ecosystem for hub and inter-hub use

Experience

• Experience using and developing flows for tools from Ansys, Cadence, Keysight, Siemens, and Synopsys tools (not all five required but experience across vendors desired)
• Experience with deployment and use of EDA tools on commercial cloud platforms
• Experience with analog and digital design
• Experience with IP module maintenance and usage

Requirements

Minimum of master’s level degree in electrical engineering, materials science, physics, or related degree covering fundamentals of microelectronics engineering principles and fabrication technologies and five years of experience with a variety of EDA flows from a variety of vendors. Experience spanning analog and digital design and IP development, usage, and maintenance.

Analog Design & Layout Engineer

The MOSIS 2.0 PIES Team is Hiring

Background

The California Defense Ready Electronics and Microdevices Superhub (California DREAMS) will promote innovation and lab-to-fab transition for RF and other technologies in the Southern California region. MOSIS 2.0 will play a critical role in providing access to university nanofabs and industry prototyping and production fabs in support of rapid prototyping for Government- and Industry-funded R&D projects. The primary end uses for the service span from advanced RF-spectrum communications and sensing applications such as 5G/6G and related domains to advanced digital design. The Prototype Integration and Engineering Services (PIES) team will operate within MOSIS 2.0 to provide engineering support for users bridging the valley between innovations and production.

This role seeks a skilled engineer who excels in one or more of the following: analog circuit/RF design, digital circuit design, and physical layout implementation. The successful candidate will work directly with MOSIS 2.0 customers to help design and layout circuits across a range of process technologies. Additionally, they will support USC’s tape out classes and contribute to funded research projects within the USC ECE department. This is an ideal opportunity for someone who enjoys blending hands-on technical work with educational and research support.

Location

California (On-site at USC/ISI in Marina del Rey, and at the USC University Park Campus)

Position Type

Full-Time, Research/Support Role, MOSIS 2.0 (California DREAMS Microelectronics Commons) / USC ECE Department.

Responsibilities

• Customer and Project Support
  • Collaborate with MOSIS 2.0 customers to develop high-quality analog circuit designs or digital circuit designs and assist customers with layout implementation.
  • Provide technical guidance on best practices for schematic capture, simulation, layout creation, and design rule compliance across various process technologies (e.g., CMOS, BiCMOS, III-V).
• Academic and Research Engagement
  • Assist in the delivery of tape out classes at USC by demonstrating layout techniques and troubleshooting common design issues.
  • Support funded research projects by providing design and layout expertise, including post-layout simulation, parasitic extraction, and layout verification.
• Technical Documentation and Collaboration
  • Prepare detailed design reports, layout closure documentation, and technical presentations for both industry and academic stakeholders.
  • Collaborate with USC faculty, students, and industry partners to continuously improve design methodologies and workflows.

Qualifications

• Educational Background
  • Bachelor’s, Master’s degree, or PhD in Electrical Engineering, Electronics, or a related field
• Technical Expertise
  • Minimum 3 years of experience in analog circuit design and/or analog layout.
  • Proficient in industry-standard CAD tools (e.g., Cadence Virtuoso, SPICE simulators, Mentor Graphics tools, or equivalent).
  • Strong understanding of layout verification methods (DRC, LVS) and parasitic extraction techniques.
  • Experience with device, electromagnetic, or photonic component simulations desired but not required.
• Interpersonal and Communication Skills
  • Excellent communication skills with the ability to work effectively with customers and academic teams.
  • Prior teaching, tutoring, or workshop facilitation experience is a plus.
• Adaptability
  • Ability to work across multiple process technologies and adapt designs to meet various manufacturing guidelines.

Semiconductor Process Engineer – Autonomous Experimentation & AI for Nanofabrication Facilities

The MOSIS 2.0 PIES Team is Hiring

Background

The California Defense Ready Electronics and Microdevices Superhub (California DREAMS) will promote innovation and lab-to-fab transition for RF and other technologies in the Southern California region. MOSIS 2.0 will play a critical role in providing access to university nanofabs and industry prototyping and production fabs in support of rapid prototyping for Government- and Industry-funded R&D projects. The primary end uses for the service span from advanced RF-spectrum communications and sensing applications such as 5G/6G and related domains to advanced digital design. The Prototype Integration and Engineering Services (PIES) team will operate within MOSIS 2.0 to provide engineering support for users bridging the valley between innovations and production.

MOSIS 2.0 PIES team is hiring a Semiconductor Process Engineer that will be part of a core team at USC/ISI complemented by a distributed team at our partner university labs and industry fabs. We are seeking a highly motivated semiconductor process engineer with a strong background in artificial intelligence (AI) and machine learning or robotics. The ideal candidate will drive the development of autonomous experimentation processes and optimize semiconductor fabrication flows at USC’s Nanofabrication Facility. This role integrates cutting-edge AI methodologies into traditional process engineering to enhance yield, efficiency, and innovation.

Location

California (On-site at the USC University Park Campus)

Position Type

Full-Time, Research/Support Role, MOSIS 2.0 (California DREAMS Microelectronics Commons) / USC ECE Department.

Responsibilities

• Process Development & Optimization
  • Design, implement, and optimize semiconductor fabrication processes by integrating AI models and machine learning algorithms.
  • Develop autonomous experimentation flows to enable real-time process control and optimization.
• Data Analysis & Automation
  • Collect, analyze, and interpret process data to identify trends and drive continuous improvement.
  • Collaborate with software developers and process engineers to create automated control platforms and reporting systems.
• Research and Collaborative Projects
  • Work closely with USC ECE department researchers and facility staff to support funded research projects in nanofabrication.
  • Contribute to technical papers, research reports, and presentations that document the integration of AI into process control.
• Training and Technical Support
  • Provide training and technical support to facility personnel on AI-enabled process control systems and autonomous workflows.
  • Assist in the troubleshooting and scaling of new process flows from laboratory settings to high-volume production.

Qualifications

• Educational Background
  • Bachelor’s, Master’s, or PhD in Electrical Engineering, Materials Science, Chemical Engineering, or a related field.
• Professional Experience
  • At least 3 years of hands-on experience in semiconductor process engineering.
  • Demonstrable experience in applying AI, machine learning, or statistical process control to manufacturing processes.
• Technical Skills
  • Proficiency in programming languages (e.g., Python, MATLAB, or R) and familiarity with machine learning frameworks.
  • Strong knowledge of semiconductor fabrication techniques (e.g., photolithography, etching, deposition, metrology).
• Analytical and Communication Skills
  • Excellent problem-solving skills and a data-driven mindset.
  • Strong written and verbal communication skills with the ability to articulate complex technical concepts to diverse audiences.
• Collaborative Spirit
  • Proven ability to work in interdisciplinary teams and support research-driven projects.