Event Details

Computing capabilities are proving to be a bottleneck in the age of machine learning. Large neural network model sizes have made data access and movement the main challenge. At UCLA, my colleagues and I have made some headway in solving this problem with a bag of diverse tools ranging from novel memory technologies, non von-Neuman architectures, high performance circuit techniques, and even unique number representations. The research has been (and is being) supported under the DARPA FRANC, LTLT, and OPTIMA programs. This talk presents an overview of our approaches and achievements in high density spintronics based memories, compute-in-memory circuits, stochastic computing, and high speed I/O design.

January 30, 2026

Join Zoom Webinar

Host: Steve Crago
POC: Amy Kasmir

Speaker Bio

Dr. Sudhakar Pamarti is a Professor of Electrical and Computer Engineering at the University of California, Los Angeles. He received the Bachelor of Technology degree from the Indian Institute of Technology, Kharagpur, and the Ph.D. degrees in electrical engineering from the University of California, San Diego. He has either worked for, consulted with, or advised, both software and hardware companies on wireless and wireline communications, and integrated circuit design. His research focuses on developing circuit and algorithmic techniques to overcome common impairments in ICs. He has served on the editorial boards and/or technical program committees of key journals and conferences of the IEEE Solid State Circuits and Circuits and System societies.