Event Details

As conventional technology scaling becomes harder, 2.5D integration provides a viable pathway to building larger systems at lower cost. Waferscale chiplet-based systems, as much as 100X larger than largest modern SoCs pose new opportunities and challenges in their architecture and design. We describe a waferscale GPU concept and discuss our experience designing a 2000 chiplet waferscale processor system, pointing out key challenges and solutions. Next, we describe our ongoing work on developing a cross-stack pathfinding framework for large distributed 2.5D/3D systems, identifying areas where technology development would help design metrics substantially, especially for the important class of distributed machine learning training applications.

June 20, 2025

Join Zoom Meeting
https://usc.zoom.us/j/97017422125?pwd=Dbrt8MNMrmBV3xalKQJcAiNsggFJjJ.1&from=addon
Meeting ID: 970 1742 2125
Passcode: 937624

Host: Steve Crago
POC: Amy Kasmir

Speaker Bio

Puneet Gupta received the B.Tech. degree in electrical engineering from the Indian Institute of Technology Delhi, New Delhi, India, in 2000, and the Ph.D. degree from the University of California at San Diego, San Diego, CA, USA, in 2007. He is currently a Faculty Member with the Electrical and Computer Engineering Department, University of California at Los Angeles. He Co-Founded Blaze DFM Inc., Sunnyvale, CA, USA, in 2004 and served as its Product Architect until 2007. He has authored over 200 papers, 18 U.S. patents, a book and two book chapters in the areas of system-technology co-optimization as well as variability/reliability aware architectures. Dr. Gupta is an IEEE Fellow and was a recipient of the NSF CAREER Award, the ACM/SIGDA Outstanding New Faculty Award, SRC Inventor Recognition Award, and the IBM Faculty Award. He currently leads the system benchmarking thrust within SRC JUMP 2.0 CHIME packaging center.